1. Field of the Invention
The present invention relates to a method of manufacturing a layered chip package that includes a plurality of stacked semiconductor chips.
2. Description of Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package including a plurality of semiconductor chips (hereinafter, also simply referred to as chips) that are stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires-hamper quick circuit operation.
The through electrode method eliminates the problems with the wire bonding method described above. However, since the through electrode method does not allow the through electrodes to be exposed in any side surface of the layered chip package, the through electrodes cannot be used as terminals of the layered chip package. Accordingly, when terminals are required at a side surface of the layered chip package, it is necessary in the through electrode method to form the terminals on the side surface of the layered chip package and also form an electrical path for electrically connecting the through electrodes to the terminals.
Given this situation, a side surface of the layered chip package may be provided with wiring including a plurality of wires for establishing electrical connection between stacked chips. In this case, the wires can also be used as terminals disposed on the side surface of the layered chip package.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
The manufacturing method disclosed in U.S. Pat. No. 5,953,588 requires a large number of steps and this raises the cost for the layered chip package. According to the method, after a plurality of chips cut out from a processed wafer are embedded into the embedding resin, a plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for the multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.
The manufacturing method disclosed in U.S. Pat. No. 7,127,807 B2 allows forming a plurality of electrically-conductive lines simultaneously on a plurality of multilayer modules included in the module stack. It is therefore possible to reduce the number of steps for forming the electrically-conductive lines as compared with the case of forming a plurality of electrically-conductive lines on one multilayer module after another. Such a method, however, involves the step of forming the electrically-conductive lines on each of a plurality of module stacks which are obtained by cutting the module array stack. The method therefore still has a large number of steps for forming the electrically-conductive lines with the problem of higher cost of the multilayer module.